{"id":4247,"date":"2025-06-20T10:04:09","date_gmt":"2025-06-20T14:04:09","guid":{"rendered":"https:\/\/smlegacy.getbeta.link\/?post_type=jobs&p=4247"},"modified":"2025-06-20T10:04:45","modified_gmt":"2025-06-20T14:04:45","slug":"concepteur-senior-asic-baseband","status":"publish","type":"jobs","link":"https:\/\/smlegacy.getbeta.link\/fr\/emplois\/concepteur-senior-asic-baseband\/","title":{"rendered":"Concepteur Senior ASIC Baseband"},"content":{"rendered":"\n

Lieu:<\/strong> Montr\u00e9al, QC<\/p>\n\n\n\n

Votre r\u00f4le<\/strong>\u00a0
En tant que Concepteur Senior ASIC Baseband, vous jouerez un r\u00f4le cl\u00e9 dans la conception et la mise en \u0153uvre des sous-syst\u00e8mes num\u00e9riques de baseband au c\u0153ur des transcepteurs UWB de SPARK. Vous travaillerez sur la conception RTL et la v\u00e9rification de blocs de traitement de signal, de contr\u00f4leurs MAC\/PHY, d\u2019interfaces \u00e0 faible latence et de logiques de contr\u00f4le sur mesure pour la communication sans fil. Vous collaborerez \u00e9troitement avec les \u00e9quipes analogique, RF, micrologicielle (firmware) et de v\u00e9rification afin de livrer des conceptions performantes et robustes.\u00a0<\/p>\n\n\n\n

Vos responsabilit\u00e9s<\/strong> <\/h2>\n\n\n\n
    \n
  • Concevoir et impl\u00e9menter du RTL pour des blocs complexes de traitement de signal num\u00e9rique de baseband (ex. : corr\u00e9lateurs, d\u00e9codeurs, filtres, moteurs de paquets, etc.)\u00a0<\/li>\n\n\n\n
  • Contribuer \u00e0 l\u2019architecture et d\u00e9finir les chemins de donn\u00e9es\/de contr\u00f4le et les interfaces num\u00e9riques de la cha\u00eene de traitement de baseband sans fil.\u00a0<\/li>\n\n\n\n
  • Assurer une int\u00e9gration \u00e9troite avec les sous-syst\u00e8mes RF, analogiques et micrologiciels.\u00a0<\/li>\n\n\n\n
  • Appliquer des principes de conception \u00e0 faible consommation d\u2019\u00e9nergie et \u00e0 faible latence (gating d\u2019horloge, optimisation des machines \u00e0 \u00e9tats, r\u00e9duction des chemins de donn\u00e9es).\u00a0<\/li>\n\n\n\n
  • Contribuer aux simulations et plans de v\u00e9rification au niveau des blocs et au niveau syst\u00e8me, et les r\u00e9viser.\u00a0<\/li>\n\n\n\n
  • Supporter la synth\u00e8se, le linting, l\u2019analyse CDC (Clock Domain Crossing) et l\u2019analyse temporelle (STA) pour vos blocs.\u00a0<\/li>\n\n\n\n
  • Analyser et d\u00e9boguer le comportement du sous-syst\u00e8me baseband \u00e0 l\u2019aide de simulations et de prototypes FPGA.\u00a0<\/li>\n\n\n\n
  • Documenter la microarchitecture et la conception.\u00a0<\/li>\n\n\n\n
  • Participer aux revues de conception et aux discussions au niveau syst\u00e8me afin de guider les futures am\u00e9liorations du baseband.\u00a0<\/li>\n\n\n\n
  • Coacher et soutenir les autres membres de l\u2019\u00e9quipe.\u00a0<\/li>\n<\/ul>\n\n\n\n

    Votre profil<\/strong> <\/h3>\n\n\n\n
      \n
    • Baccalaur\u00e9at ou ma\u00eetrise en g\u00e9nie \u00e9lectrique ou informatique (ou \u00e9quivalent).\u00a0<\/li>\n\n\n\n
    • Plus de 10 ans d\u2019exp\u00e9rience en conception ASIC ou FPGA, avec une expertise sur le traitement de signal num\u00e9rique baseband ou sans fil.\u00a0<\/li>\n\n\n\n
    • Ma\u00eetrise de la conception RTL en VHDL et\/ou Verilog et\/ou SystemVerilog.\u00a0<\/li>\n\n\n\n
    • Excellente compr\u00e9hension des syst\u00e8mes de communication num\u00e9rique (modulation, d\u00e9modulation, correction d\u2019erreurs, r\u00e9cup\u00e9ration temporelle, \u00e9galisation, etc.).\u00a0<\/li>\n\n\n\n
    • Exp\u00e9rience en conception et int\u00e9gration de logique num\u00e9rique MAC\/PHY pour des protocoles sans fil.\u00a0<\/li>\n\n\n\n
    • Exp\u00e9rience pratique avec les outils de v\u00e9rification RTL et les environnements de simulation (ModelSim, VCS, etc.).\u00a0<\/li>\n\n\n\n
    • Bonne connaissance des techniques de synth\u00e8se, de fermeture temporelle et d\u2019optimisation de la consommation \u00e9nerg\u00e9tique.\u00a0<\/li>\n\n\n\n
    • \u00c0 l\u2019aise dans un environnement dynamique de type startup et capable de collaborer avec des \u00e9quipes multidisciplinaires.\u00a0<\/li>\n<\/ul>\n\n\n\n

      Atouts<\/strong> <\/h3>\n\n\n\n
        \n
      • Exp\u00e9rience avec les standards sans fil (UWB, BLE, ZigBee, etc.).\u00a0<\/li>\n\n\n\n
      • Exp\u00e9rience avec Python pour la mod\u00e9lisation du traitement de signal.\u00a0<\/li>\n\n\n\n
      • Familiarit\u00e9 avec les outils de validation et de d\u00e9bogage post-silicium.\u00a0<\/li>\n\n\n\n
      • Connaissance des techniques de conception \u00e0 tr\u00e8s faible consommation et des interfaces asynchrones.\u00a0<\/li>\n<\/ul>\n\n\n\n

        Les Avantages<\/strong> <\/h3>\n\n\n\n
          \n
        • Une start-up en pleine croissance o\u00f9 chaque personne a un r\u00f4le important \u00e0 jouer dans le succ\u00e8s de l\u2019entreprise.\u00a0<\/li>\n\n\n\n
        • Faire partie d\u2019une \u00e9quipe passionn\u00e9e, cr\u00e9ative et motiv\u00e9e en mode collaboratif.\u00a0<\/li>\n\n\n\n
        • Un endroit o\u00f9 vous pouvez grandir et devenir le professionnel que vous voulez \u00eatre.\u00a0<\/li>\n\n\n\n
        • Assurance collective d\u00e8s le premier jour.\u00a0<\/li>\n\n\n\n
        • Plan d\u2019options d\u2019achat d\u2019actions pour les employ\u00e9s.\u00a0<\/li>\n\n\n\n
        • Une vie sociale active \u2013 \u00e9v\u00e8nements\/activit\u00e9s, pause-caf\u00e9, lunch and learns, et plus!\u00a0<\/li>\n\n\n\n
        • Travail hybride et journ\u00e9es de travail \u00e0 la maison pour concilier travail et vie personnelle.\u00a0<\/li>\n\n\n\n
        • En plus des vacances, des cong\u00e9s de maladie et des jours f\u00e9ri\u00e9s, SPARK offre des jours de cong\u00e9 suppl\u00e9mentaires.\u00a0<\/li>\n\n\n\n
        • Tracances \u2013 Prolonger vos vacances \u00e0 l\u2019\u00e9tranger et travailler deux semaines par ann\u00e9e \u00e0 distance.\u00a0<\/li>\n<\/ul>\n\n\n\n

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